Metadata-Version: 2.4
Name: routertl
Version: 0.0.1
Summary: The full-vertical FPGA SDK. Define once in YAML. Simulate, synthesize, and ship — across Xilinx, Intel, and Lattice — from one terminal.
Author-email: "Daniel J. Mazure" <daniel@dmazure.com>
License: MIT
Project-URL: Homepage, https://github.com/djmazure/routertl
Keywords: fpga,vhdl,verilog,simulation,synthesis,cocotb,eda,rtl
Classifier: Development Status :: 1 - Planning
Classifier: Intended Audience :: Developers
Classifier: License :: OSI Approved :: MIT License
Classifier: Programming Language :: Python :: 3
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Requires-Python: >=3.9
